1. Field of Invention
The present invention relates to a method for fabricating an electronic device, more particularly, to a method for fabricating a semiconductor device.
2. Description of Related Art
In order to accelerate operating speed of integrated circuit and to meet customers' demands on miniaturizing electronic devices, physical dimensions of transistors in a semiconductor device are continuously reduced. However, as the dimension of the transistor is reduced, its channel length will also decrease with ease leading to problems such as short channel effect and decrease in turn-on current. A conventional solution to said issue is to enhance the dopant concentration in the channel region. Nevertheless, this method causes an increase in a leakage current and therefore affects the reliability of devices.
To resolve said issue, the conventional horizontal transistor structure is recently replaced by a vertical transistor structure in the industry. For example, the vertical transistor structure is formed in a deep trench of the substrate. Hence, the operating speed and integration level of integrated circuits are enhanced and problems such as short channel effect are avoided. However, the coupling effect between the adjacent conductive regions (e.g., heavily doped silicon) becomes more and more serious in the conventional vertical transistor, and the issue such as parasitic capacitance is also arising.